The preferred way of providing output on today's personal computers ("PCs") is by way of a video display. A video display allows a PC to display data for the benefit of a user in a temporary, rapidly mutable fashion. A video display is coupled to a microprocessor central processing unit ("CPU") of the PC via a video controller, allowing the CPU to send data to the video display. The video controller acts as a translator or interface, receiving logic signals from the CPU and generating corresponding video driver signals in response thereto.
It is common practice to provide a memory-mapped video display in PC architectures. In memory mapping, a portion of the PC's memory is designated as video memory, dedicated to storing data to be displayed on the video display. Specific, individually-addressable locations within the video memory correspond to individual pixels, or "picture elements," on the video display. In a memory-mapped PC, the CPU writes the data to be displayed to the video memory. The video controller scans the video memory, sending video driver signals to the video display based on the contents of the video memory. Although video memory appears no different than other memory to the CPU, video memory is "dual port," allowing access from one side by the CPU and access from another side by the video controller Alternatively, single ported DRAM may be used in configurations where the CPU accesses the DRAM through a video controller.
Video memory is conventionally available in the form of plug-in modules comprising a circuit board having video memory chips located thereon and adapted to be installed in a slot of the computer as a daughter-card. The modular construction of the video memory allows for ease of installation and a number of different memory sizes and logical configurations.
The video controller accesses the video memory by scanning it address by address. Since the video memory corresponds to the cartesian arrangement of pixels on the video display, the video controller is thought of as scanning the video memory column by column and row by row. The video controller uses a video memory clock to control the rate at which it scans the video memory. The video memory clock provides the timing to generate control signals, such as row address strobe ("RAS") and column address strobe ("CAS"), to the video memory.
In the past, video controllers were driven by clock signal from a video memory clock having a single frequency. In prior art computers, the video memory clock was set to a certain frequency during manufacture and was not changeable. Frequently, video controllers in these prior art computers were provided with the capability of operating in a number of different video modes, depending upon the size and logical configuration of the video memory, such as modes in which the video memory is scanned in an interleaved manner. Each mode typically yields optimum performance at a different clock frequency.
For example, interleaving is only possible when two banks of memory are present. This requires a fairly large amount of memory. Interleaving also requires stricter timings. Thus, the video clock frequency must be lowered to allow sufficient timing tolerance. If non-interleaved memory is used in a computer in which the video clock frequency has been lowered to accommodate interleaved memory, performance of the non-interleaved memory configuration suffers, since the video memory clock frequency could be set at a faster rate.
Unfortunately, since the prior art video memory clocks were of single frequency, the frequency had to be set as high as possible, although not exceeding the highest allowed frequency of any given mode, resulting in a frequency compromise. Thus, while some slower video modes were driven at their limits, faster modes were underdriven, resulting in relatively poor performance.
Some manufacturers enhanced performance of the faster modes by increasing clock frequency. However, they did so at the risk of driving the slower modes outside of the normal operating ranges of components in the video controller, bringing about a chance of failures.
What is needed in the art are a circuit and method for detecting video memory configuration and for adjusting the frequency of the video memory clock as a function thereof, allowing the video display to operate at optimum performance in every one of several possible video memory configurations and video modes.